In general, a write operation of a semiconductor memory device refers to an operation of finally storing data, inputted from a data pad, in a memory cell through a global line and a local line. Here, the data inputted from the data pad is driven by a global line driver and transmitted to the global line, and the data inputted through the global line is driven by a write driver and transmitted to the local line.
FIG. 1 is a timing diagram explaining a write operation of a known semiconductor memory device.
When an external write command ECASP_WT is inputted at a time point T1, a write pulse WTP is generated at a time point T2 where one cycle of a first internal clock signal FCLKB passes. After a burst start signal LCWT generated by clock-shifting the write pulse WTP is enabled, an input control signal DINSTB is enabled. Here, the input control signal DINSTB is a signal for enabling a global line driver. After the input control signal DINSTB is enabled to a logic high level, the global line driver transmits data DATA inputted from a data pad to a global line.
Furthermore, at a time point T3, a write driver enable signal BWEN is generated after the burst start signal LCWT is enabled. Here, the write driver enable signal BWEN is a signal for enabling a write driver. When the write driver enable signal BWEN is enabled to a logic high level, the write driver transmits the data DATA inputted through the global line to a local line.
However, when the global line has a large loading level, the data DATA is delayed by a period A. Therefore, since the write driver cannot transmit the data DATA to the local line at a time point where the write driver enable signal BWEN is enabled, a write fail occurs.